Designs

SM802, SM803, SM806, SM813 Clock Generation Family

Select Device:

Let Clockworks Choose Device

SM806 < 100fs jitter; Smallest package; Single PLL; Max 6 output

SM813 < 150fs jitter; Dual PLL; Max 8 output

SM802 < 300fs jitter; Single PLL; Max 8 output

SM803 < 200fs jitter; Low jitter; Dual PLL; Max 12 output

Output Frequency:

Enter up to 12 output frequencies and ClockWorks will assign the optimal product family to your design (SM806,SM802, SM803, or SM813). Output frequency range is 12.5MHz to 850MHz for differential output formats and 12MHz to 250MHz for LVCMOS output format, precision up to 6 decimal places (MHz).
Please note, all output formats are by default LVPECL. They can be modified in the design page (next 2 pages).




Output Enable (OE) (SM813: required)	FSEL Allows second frequency per bank You can enter FSEL values in the following forms Not available for SM813	OE and FSEL apply to every active output/bank. You can check/uncheck them per individual output/bank in the next forms.